Intel Introduces Intel 18A-P Node with Major Performance and Efficiency Gains

At the recent VLSI Symposium in Hawaii, Intel announced the launch of its advanced Intel 18A-P foundry node, marking a significant evolution from the original Intel 18A process. This new node delivers a notable 9% performance boost at iso-power, positioning it as a key technology for next-generation data center and server applications. Intel has already begun risk production of Intel 18A-P and confirmed its use in the upcoming Xeon "Diamond Rapids" server processors.

Key Improvements in Intel 18A-P Technology

Intel 18A-P introduces several enhancements over its predecessor, focusing on both performance and energy efficiency. The node offers:

  • 9% higher performance at iso-power
  • 18% reduction in power consumption at iso-performance
  • 20-40% improvement in die-level thermal resistance
  • 10-30% reduction in via resistance in performance-critical layers

These advancements are achieved through a series of physical and architectural changes. Intel expanded its cell library, adding new options to the 180HP and 160HD libraries to support a broader range of product requirements. For low-power applications, the W1 and W1.5 cells have been introduced, while high-performance designs benefit from the new W3P cell. The W3P cell features a "dual contact" design, enhancing performance without increasing the footprint compared to the existing W3 cell.

Thermal management has also been significantly improved. Intel integrated a new heat-conducting material on the front side of the die, resulting in lower thermal resistance. Additionally, updated EDA tools now support thermally-aware layouts, enabling designers to optimize heat dissipation at the structural level.

Diamond Rapids: Next-Generation Xeon Built on Intel 18A-P

The first product to leverage the Intel 18A-P node will be the Xeon 7 "Diamond Rapids" server processor. This processor adopts a chiplet-based architecture, similar to the approach used by AMD EPYC, where CPU cores are distributed across smaller chiplets built on advanced nodes and connected to centralized I/O resources. This design ensures more uniform memory latency across all CPU cores.

"Diamond Rapids" features four Compute tiles, also referred to as core building blocks (CBBs), each manufactured on the Intel 18A-P node. Each Compute tile contains a CPU complex with 48 "Panther Cove" performance cores (P-cores) and localized L3 cache. In total, the processor offers 192 cores and 192 threads, as simultaneous multithreading (SMT) is not implemented.

The Compute tiles communicate with two I/O and Memory Hub (IMH) tiles, which are built on a mature foundry node such as Intel 3. Each IMH tile supports an 8-channel DDR5 memory interface, providing a total of 16 DDR5 channels per package. "Diamond Rapids" is also Intel’s first processor to support PCI Express Gen 6, which doubles the bidirectional bandwidth compared to PCIe Gen 5, although specific PCIe lane counts have not been disclosed.

Advanced Packaging and Platform Innovations

To accommodate the high core count and advanced features, "Diamond Rapids" is built on a large substrate and introduces the new LGA9324 socket, which features a substantial pin count to support the processor’s capabilities.

The Intel Xeon 7 "Diamond Rapids" family is scheduled for market release in 2027, representing a major step forward in server processor technology and manufacturing innovation.